1. Technical Field
The present disclosure relates, in general, to non-volatile semiconductor memory devices and, more particularly, to a non-volatile semiconductor memory device to minimize skew and reduce chip layout area, and a method of driving the same.
2. Discussion of the Related Art
Generally, a non-volatile semiconductor memory device includes a memory array having a plurality of memory cells, page buffers, and data lines. The memory cells receive or transmit data through their respective bit lines. The page buffers latch data corresponding to voltage levels of the bit lines. The page buffers also transmit or receive data to or from the data lines. The data lines typically transmit or receive data to or from data pads arranged on one side of the non-volatile semiconductor memory device.
FIG. 1 illustrates a conventional non-volatile semiconductor memory device. In FIG. 1, a memory array 10 includes a plurality of bit line groups BL<1> to BL<8>. Each of the bit line groups BL<1> to BL<8> may be implemented using a single bit line or two bit lines forming a pair. Although not shown in the drawing, each of the bit line groups BL<1> to BL<8> is connected to a plurality of memory cells. The bit line groups BL<1> to BL<8> are connected to corresponding page buffers PB<1> to PB<8>, respectively. The page buffers PB<1> to PB<8> are connected to a data input/output (I/O) unit 50 through corresponding data lines DL<1> to DL<8>.
For convenience of layout, respective page buffers PB<1> to PB<8> are alternately arranged above and below the memory array 10. However, the data I/O unit 50 is arranged on one side of the memory array 10 (in FIG. 1, below the memory array).
In the conventional non-volatile semiconductor memory device of FIG. 1, the data lines DL<1>, DL<3>, DL<5> and DL<7>, connected to the page buffers PB<1>, PB<3>, PB<5> and PB<7>, which are arranged below the memory array 10, have a relatively short bus length. However, the data lines DL<2>, DL<4>, DL<6>and DL<8>, connected to the page buffers PB<2>, PB<4>, PB<6> and PB<8>, which are arranged above the memory array 10, have a relatively long bus length.
Therefore, during the transmission of data, skew occurs between the lower page buffers PB<1>, PB<3>, PB<5> and PB<7> and the upper page buffers PB<2>, PB<4>, PB<6> and PB<8>. Further, a large layout area is required for wiring between the upper page buffers PB<2>, PB<4>, PB<6> and PB<8> and the data I/O unit 50.
There is a need for a non-volatile semiconductor memory device that can minimize skew and reduce chip layout area.